Lead C++ Software Engineer At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for an exceptional C++ software engineer to join the Protium Software Development Team to develop and enhance the Protium FPGA-Based Prototyping product which is used by leading CPU/GPU/HyperScaler companies for pre-Silicon software validation of their SOC’s. You will develop new algorithms and optimizations for QoR (Quality of Results) and performance for the Protium Compiler working with a small team of super star engineers to develop our next generation FPGA based verification platform. Responsibilities: Enhance Static Timing Analysis (STA) in the Protium Compiler. Work includes implementing new algorithms in C++ to support Multi-cycle constraints and other SDC exceptions such as set_false_path. Optimize memory and runtime by using multi-threading and distributed computing. Develop the EDA automation flow for the platform with other engineers. Write Design Specifications and Unit Tests for your code. Position Requirements/Qualifications: Bachelors in Computer Science, Electrical/Computer Engineering and a minimum of 4 years of related experience, or Masters and a minimum of 2 years of related experience, or PhD with thesis in a relevant area. Ideally you are a solid contributor in the FPGA or ASIC prototyping/synthesis/verification space and have delivered great QoR on these platforms. You are well renowned for your excellent programming skills in C/C++ and you document your work clearly and love talking about it to your team. You are very comfortable with Verilog or SystemVerilog and understand digital circuits. Usage of popular logic simulators and some experience in multi-threaded/concurrent programming are pluses. The role requires exceptional software skills and Object Oriented Programming experience to be a good match. Knowledge and experience of ML/AI algorithms and deployment in production code a plus. We’re doing work that matters. Help us solve what others can’t. Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers to create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. #J-18808-Ljbffr Read More Read Less
Lead C++ Software Engineer Locations: TORONTO Time Type: Full time Posted on: Posted 30+ Days Ago Job Requisition ID: R44832 At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for an exceptional C++ software engineer to join the Protium Software Development Team to develop and enhance the Protium FPGA-Based Prototyping product which is used by leading CPU/GPU/HyperScaler companies for pre-Silicon software validation of their SOC’s. You will develop new algorithms and optimizations for QoR (Quality of Results) and performance for the Protium Compiler working with a small team of super star engineers to develop our next generation FPGA based verification platform. Responsibilities: Enhance Static Timing Analysis (STA) in the Protium Compiler. Work includes implementing new algorithms in C++ to support Multi-cycle constraints and other SDC exceptions such as set_false_path. Optimize memory and runtime by using multi-threading and distributed computing. Develop the EDA automation flow for the platform with other engineers. Write Design Specifications and Unit Tests for your code. Position Requirements/Qualifications: Bachelors in Computer Science, Electrical/Computer Engineering and a minimum of 4 years of related experience, or Masters and a minimum of 2 years of related experience, or PhD with thesis in a relevant area. Ideally you are a solid contributor in the FPGA or ASIC prototyping/synthesis/verification space and have delivered great QoR on these platforms. You are well renowned for your excellent programming skills in C/C++ and you document your work clearly and love talking about it to your team. You are very comfortable with Verilog or SystemVerilog and understand digital circuits. Usage of popular logic simulators and some experience in multi-threaded/concurrent programming are pluses. The role requires exceptional software skills and Object Oriented Programming experience to be a good match. Knowledge and experience of ML/AI algorithms and deployment in production code a plus. We’re doing work that matters. Help us solve what others can’t. We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known. Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. #J-18808-Ljbffr Read More Read Less
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Overview: This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The candidate will primarily be responsible for leading a team of engineers in the verification of digital RTL and development of re-usable verification components and environments. The successful candidate will be a highly motivated self-starter with strong leadership qualities. It is also expected that the candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure. The ideal candidate will have a fundamental understanding of the end-to-end verification flow in order to accurately and efficiently communicate with all members of the technical staff regarding overall project development progress and status. The most successful candidates will be able to demonstrate excellent command of fundamental logic principles as well as excellent problem-solving and communication skills. The candidate should be able to work as part of a focused team of engineers and collaborate successfully as needed with design teams, verification teams, project management, and digital and analog design teams in multiple worldwide geographies. The Cadence Silicon Solutions Group (SSG) develops leading edge Intellectual Property (IP) for a variety of High-Tech Markets. Job Responsibilities: Project planning and progress tracking Leading a team of 5-15 engineers in the execution of verification tasks Definition and Management of Verification Plans (vPlans) using Cadence vManager tools Architecture of Verification Environments for complex IP such as Multi-protocols PHY Development of UVM-SV Scoreboards for self-checking regressions Development of Functional Coverage as part of Metric Driven Verification Environments Development of SystemVerilog Assertions for use in Formal and Simulation Environments Creation and Management of Automated Regression Environments, e.g. Jenkins Participation in Technical Review Meetings and Checklist Reviews Close Collaboration with Design Engineers to debug complex test scenarios Job Qualifications: Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline 12+ years’ experience in microelectronics/EDA industry Experience of Verilog RTL Design essential Experience of Metric Driven Verification (MDV) essential Excellent oral and written English essential Exposure to Standard Protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI Self-motivated with excellent planning, interpersonal, and communication skills Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. Travel: Be proud and passionate about the work you do. Together, our One Cadence -- One Team culture drives our success. We’re doing work that matters. Help us solve what others can’t. We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known. #J-18808-Ljbffr Read More Read Less
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for an exceptional C++ software engineer to join the Protium Software Development Team to develop and enhance the Protium FPGA-Based Prototyping product which is used by leading CPU/GPU/HyperScaler companies for pre-Silicon software validation of their SOC’s. You will develop new algorithms and optimizations for QoR (Quality of Results) and performance for the Protium Compiler working with a small team of super star engineers to develop our next generation FPGA based verification platform. Responsibilities: Enhance Static Timing Analysis (STA) in the Protium Compiler. Work includes implementing new algorithms in C++ to support Multi-cycle constraints and other SDC exceptions such as set_false_path. Optimize memory and runtime by using multi-threading and distributed computing . Develop the EDA automation flow for the platform with other engineers. Write Design Specifications and Unit Tests for your code Position Requirements/Qualifications: Bachelors in Computer Science, Electrical /Computer Engineering and a minimum of 4 years of related experience, or Masters and a minimum of 2 years of related experience, or PhD with thesis in a relevant area. Ideally you are a solid contributor in the FPGA or ASIC prototyping/synthesis/verification space and have delivered great QoR on these platforms. You are well renowned for your excellent programming skills in C/C++ and you document your work clearly and love talking about it to your team. You are very comfortable with Verilog or SystemVerilog and understand digital circuits . Usage of popular logic simulatorsand some experience in multi-threaded/ concurrent programming are pluses. The role requires exceptional software skills and Object Oriented Programming experience to be a good match Knowledge and experience of ML / AI algorithms and deployment in production code a plus We’re doing work that matters. Help us solve what others can’t. We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known. #J-18808-Ljbffr Read More Read Less
Principal Design Engineer Apply locations: TORONTO Time Type: Full time Posted on: Posted 3 Days Ago Job Requisition ID: R49005 At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This team is focused on High Speed Serdes. The ideal candidate will have at least 5 plus years of actual work experience in SerDes as well as a thorough understanding of the end-to-end digital design flow to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status. This includes but is not limited to: Digital microarchitecture definition and documentation RTL logic design, debug and functional verification Understanding of digital architecture trade-offs for power, performance, and area Understanding of proper handling of multiple asynchronous clock domains and their crossings Understanding of Lint checks, UPF checks and proper resolution of errors Understanding synthesis timing constraints, static timing analysis and constraint development Understanding of fundamental physical design flows and stages Understanding of wireline standards and collaborating with standards experts to relate standard requirements to logic specifications Experience on silicon bring-up and testing of wireline IP Strong background in DSP and algorithms is a plus Requested Skill Set Master’s degree or higher in Electrical Engineering Minimum 5 years of digital design work experience Hands-on experience in implementing and demonstrating digital designs in FPGAs or ICs We’re doing work that matters. Help us solve what others can’t. We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known. Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers to create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. #J-18808-Ljbffr Read More Read Less
